How to design a PCB for dual screen HDMI to MIPI DSI adapter?

How to Design a PCB for Dual Screen HDMI to MIPI DSI Adapter

To design a PCB for a dual screen HDMI to MIPI DSI adapter, you need to start with a clear understanding of the signal path: HDMI input, bridging chip, MIPI DSI output, and power management. The core challenge is handling two independent MIPI DSI interfaces from a single HDMI source, which requires a bridge IC like the LT6911C or similar, capable of splitting HDMI into two MIPI DSI streams. This isn’t a trivial task—you’re dealing with high-speed differential pairs, impedance matching, and tight timing constraints. Let’s break down the practical steps, component choices, and layout rules based on real-world engineering data.

1. Selecting the Bridge IC and Understanding Its Capabilities

The bridge IC is the brain of the adapter. For dual screen support, you need a chip that can output two independent MIPI DSI lanes. The LT6911C from Lontium is a popular choice because it supports HDMI 1.4 input (up to 4K@30Hz) and can output two MIPI DSI channels, each with up to 4 data lanes plus clock. Another option is the TC358870XBG from Toshiba, which also handles dual DSI but with slightly different power sequencing. Key specs to check: maximum pixel clock (typically 340 MHz for HDMI 1.4), MIPI DSI data rate per lane (up to 1 Gbps per lane), and supported resolutions. For dual 1080p@60Hz screens, each DSI channel needs about 1.5 Gbps total bandwidth, so 4 lanes at 1 Gbps each gives you headroom. The bridge IC datasheet will specify the exact MIPI D-PHY electrical parameters, like differential voltage swing (200 mV to 1.2 V) and common mode voltage (around 200 mV).

2. Power Delivery Network (PDN) Design

Power integrity is critical for high-speed signals. The bridge IC typically requires multiple voltage rails: 1.2V for core, 1.8V for I/O, and 3.3V for HDMI and MIPI termination. Each rail needs low-noise LDOs or switching regulators with ripple below 10 mV peak-to-peak. For dual screen operation, the total current draw can exceed 1.5A on the 1.2V rail, so use a switching regulator like the TPS62130 (efficiency >90%) with proper output capacitance. Place decoupling capacitors (0.1 µF, 1 µF, and 10 µF) within 2 mm of each power pin, and use a dedicated power plane layer. The HDMI input also needs 5V power from the source, which you can regulate down to 3.3V via a linear regulator if the current is under 500 mA. For the MIPI DSI outputs, each lane termination requires 50-ohm resistors to ground, which draw about 10 mA per lane at 1.2V swing—so 8 lanes (two screens) add 80 mA. Use a 4-layer PCB stackup: top signal, ground plane, power plane, bottom signal. This minimizes loop inductance and provides a reference plane for impedance control.

3. HDMI Input Routing and Impedance Control

HDMI uses four differential pairs (TMDS data channels 0, 1, 2, and clock), each with a characteristic impedance of 100 ohms differential (50 ohms single-ended). On the PCB, route these pairs with controlled impedance: for a standard FR4 substrate (εr=4.5, thickness 1.6 mm), a 50-ohm trace width is about 0.3 mm on the top layer with a 0.2 mm gap for differential pairs. Keep the trace length mismatch under 0.5 mm (about 3 ps skew) to avoid jitter. The HDMI connector should be placed near the bridge IC to minimize stub length—ideally under 20 mm. Use AC coupling capacitors (0.1 µF, 0402 package) in series with each TMDS line, placed within 10 mm of the connector. The HDMI DDC (I2C) and HPD (hot plug detect) lines are low-speed but still need filtering: add 100 pF capacitors to ground on HPD to prevent noise. For ESD protection, use TVS diodes like the PESD5V0S1UB with 5V breakdown voltage, placed directly at the HDMI port.

4. MIPI DSI Output Routing and Lane Configuration

Each MIPI DSI interface has a clock lane and up to 4 data lanes, all differential with 100-ohm impedance. The MIPI D-PHY specification requires a maximum skew between lanes of 0.2 UI (unit interval), which at 1 Gbps is 200 ps. So route all lanes for one screen with matched lengths—keep the difference under 0.5 mm. Use serpentine traces to adjust lengths, but avoid sharp corners (use 45-degree bends). The MIPI signals are typically 1.2V differential, so they need a reference ground plane directly underneath. For dual screens, you have two separate connectors: one for each display. Common connectors are 0.5 mm pitch FPC (like FH12-40S-0.5SH) or 0.3 mm pitch for compact designs. Each connector should have a dedicated ground pin for every signal pin to reduce crosstalk. The maximum trace length from bridge IC to connector should be under 100 mm to minimize signal degradation. Add series termination resistors (0 ohm or 10 ohm) near the bridge IC for each MIPI lane to dampen reflections—these can be adjusted based on SI simulations.

5. Clock Generation and Synchronization

The bridge IC needs a reference clock for the HDMI input and MIPI output. Most chips use a 25 MHz crystal oscillator (XO) with ±25 ppm stability. For dual screen operation, the internal PLL generates the MIPI bit clock from this reference. Use a low-jitter XO like the SiT8208 (jitter < 0.5 ps RMS) to avoid phase noise. The crystal layout is critical: keep the traces short (under 10 mm), place load capacitors (typically 18 pF) close to the chip, and isolate the oscillator from noisy power lines. If the bridge IC supports spread spectrum clocking (SSC), enable it to reduce EMI—this is common in HDMI to MIPI adapters. The MIPI clock lane must be routed with the same impedance as data lanes, and its length should match the longest data lane within 0.5 mm.

6. PCB Stackup and Material Selection

For a dual screen adapter, a 4-layer board is the minimum, but 6 layers are better for signal integrity. Recommended stackup: Layer 1 (top) – signals and components; Layer 2 – ground plane; Layer 3 – power plane (split into 1.2V, 1.8V, 3.3V); Layer 4 – bottom signals. Use FR4 with a glass transition temperature (Tg) of 170°C or higher to handle soldering and thermal stress. The dielectric constant (εr) should be stable at 4.2-4.5, and the dissipation factor (Df) below 0.02 for high-speed signals. For impedance control, specify a tolerance of ±10% on the differential impedance. The board thickness is typically 1.6 mm, but for thinner connectors, 1.0 mm might be needed. Use ENIG (Electroless Nickel Immersion Gold) finish for flat pads and good solderability, especially for fine-pitch ICs like QFN packages (0.5 mm pitch).

7. Thermal Management and Component Placement

The bridge IC can dissipate 1-2W depending on resolution and lane count. Use a thermal pad on the bottom of the QFN package, connected to a ground plane with thermal vias (0.3 mm diameter, 0.5 mm pitch). Place these vias directly under the IC’s exposed pad, and connect them to the inner ground plane. For dual screen operation, the IC might run hotter, so add a small heatsink if ambient temperature exceeds 50°C. Keep the HDMI connector and MIPI connectors on opposite sides of the board to separate input and output signals. Place the power regulators near the bridge IC to minimize IR drop, but keep them away from the MIPI traces to avoid noise coupling. The crystal oscillator should be within 5 mm of the bridge IC’s clock input pin. Use a 4-pin header for programming the bridge IC (I2C or SPI) during development—this is often needed for configuration registers.

8. Signal Integrity (SI) and Electromagnetic Interference (EMI) Mitigation

High-speed signals require careful SI analysis. For HDMI, the TMDS signals have a rise time of about 100 ps, so the trace length should be under 200 mm to avoid transmission line effects. Use a 2D field solver to calculate the exact trace width for 100-ohm differential impedance. For MIPI, the data rate is up to 1 Gbps, so the rise time is around 150 ps. Add ground stitching vias along the MIPI trace edges to reduce EMI—place them every 5 mm. Use a ferrite bead on the HDMI 5V line to filter high-frequency noise. The entire board should have a solid ground plane with no splits under high-speed traces. For EMI compliance, the MIPI connectors should be shielded, and the HDMI connector should have a metal shell connected to chassis ground via a 1 nF capacitor. Add a common mode choke on the HDMI differential pairs if the design fails radiated emissions testing.

9. Configuration and Firmware Considerations

The bridge IC often requires initialization via I2C or SPI to set the MIPI DSI parameters like lane count, resolution, and refresh rate. For dual screens, you need to configure each DSI channel independently. The LT6911C, for example, has internal registers for EDID emulation, which lets you define the display resolution. You might need an external EEPROM (like 24C02) to store the configuration. The I2C bus for programming should be isolated from the HDMI DDC bus to avoid conflicts. Use pull-up resistors (4.7 kΩ) on both I2C lines. During layout, keep the I2C traces short (under 50 mm) and away from high-speed lines. Some bridge ICs support auto-detection of the display’s resolution via the MIPI DSI readback, but this is not always reliable—so pre-configure the EDID for common resolutions like 1920x1080@60Hz or 1280x720@60Hz.

10. Testing and Validation

After assembly, test the adapter with a known HDMI source and two MIPI DSI displays. Use an oscilloscope with a 1 GHz bandwidth to check the HDMI TMDS eye diagram—the eye opening should be at least 70% of the unit interval. For MIPI, measure the differential voltage swing (should be 200-400 mV) and common mode voltage (100-300 mV). Check the clock jitter with a phase noise analyzer—it should be under 10 ps RMS. Power the board with a 5V supply and measure the current draw: for dual 1080p screens, expect around 1.5A total. If the screens flicker or show artifacts, check the MIPI lane matching and termination resistors. Use a thermal camera to verify the bridge IC temperature stays below 85°C. For production, you’ll need to program the bridge IC’s firmware via a dedicated programmer, which can be done through the I2C header.

For a practical example of a working design, you can reference the dual screen hdmi to mipi dsi adapter from DisplayModule, which uses a similar architecture with the LT6911C and supports dual 1080p displays. The PCB layout in that product uses a 6-layer board, with HDMI on one side and two MIPI connectors on the other, and includes a dedicated power management section with LDOs for noise-sensitive rails. The key takeaway is that careful impedance control, power integrity, and thermal management are non-negotiable for reliable dual screen operation. Don’t overlook the MIPI DSI lane alignment—mismatch by even 1 mm can cause data errors at high speeds. Also, consider the mechanical constraints: the FPC connectors need a stiffener to prevent damage during insertion, and the board outline should fit within the enclosure’s dimensions, typically 50x80 mm for a compact design. The HDMI connector’s mounting holes should be grounded for EMC, and the entire assembly should be tested for electrostatic discharge (ESD) up to 8 kV contact discharge. If you’re designing for automotive or industrial use, add conformal coating to protect against humidity and dust. The bridge IC’s datasheet will have specific layout guidelines—follow them to the letter, especially for the MIPI D-PHY region, which is the most sensitive part of the design. For dual screens, the bridge IC must support dual DSI channels simultaneously, which some chips do via a time-division multiplexing scheme—check the datasheet for the maximum combined resolution. For example, the LT6911C can handle up to 4K@30Hz on a single screen, but when split into dual screens, each channel is limited to 1080p@60Hz. This is because the internal PLL bandwidth is shared. If you need higher resolutions, look for a chip with a faster pixel clock, like the LT6911UXC which supports HDMI 2.0 (up to 4K@60Hz) and dual 4K@30Hz MIPI outputs. The power consumption scales linearly with resolution—at 4K@60Hz, the bridge IC can draw up to 3W, so a heatsink is mandatory. The MIPI DSI cable length also matters: for a 0.5 mm pitch FPC, keep the cable under 150 mm to avoid signal degradation. If you need longer cables, use a repeater chip like the SN65LVDS315 on each MIPI channel. Finally, always prototype the design with a 2-layer board first to verify the bridge IC’s configuration, then move to a multi-layer board for production. This saves time and cost, especially if you’re experimenting with different displays. The MIPI DSI standard allows for both command mode and video mode—for HDMI adapters, video mode is used, which requires continuous clocking. Make sure the bridge IC’s firmware is set to video mode, or the display won’t sync. The EDID data from the HDMI source must match the MIPI display’s timing, which you can program via the bridge IC’s registers. For dual screens, the EDID is typically shared, meaning both displays get the same resolution—so choose displays with identical specs to avoid issues. If you need different resolutions, you’ll need a more complex bridge IC with independent EDID emulation, which is rare in consumer chips. The PCB layout should also include test points for all power rails and I2C lines, so you can debug issues during prototyping. Use a 0.1-inch header for these test points, and label them clearly on the silkscreen. The MIPI DSI connectors should have a locking mechanism to prevent accidental disconnection, like the Hirose FH12 series with a flip-lock actuator. For the HDMI connector, use a type A receptacle with a metal shield that has ground tabs soldered to the PCB. The entire board should be designed to fit within a standard enclosure, like a 100x60 mm aluminum box, with ventilation holes near the bridge IC. If you’re mass-producing the adapter, consider using a panelized PCB with a 10x10 cm array to reduce costs. The stencil for solder paste should be 0.12 mm thick for fine-pitch components. Reflow soldering with a lead-free profile (peak temperature 245°C) is standard. After assembly, perform a visual inspection under a microscope to check for solder bridges, especially on the QFN package. Then, run a functional test with a known-good HDMI source and two MIPI displays—if both screens show the same image, the adapter is working. If only one screen works, check the MIPI lane assignment and the bridge IC’s register settings. The I2C bus can be used to read back the status registers, which will indicate if the PLL is locked and the MIPI lanes are active. This is a robust way to diagnose issues without an oscilloscope. For production testing, you can automate the I2C readback with a microcontroller like the STM32F103, which sends commands and checks the response. This ensures every unit meets the specifications. The design can be scaled to support more than two screens by using a bridge IC with multiple MIPI outputs, but the PCB complexity increases significantly due to the additional routing and power requirements. For now, dual screen is the most common configuration for industrial and medical applications, where two displays show the same information for redundancy or different angles. The adapter can also be used in automotive head-up displays (HUDs) where two screens are needed for driver and passenger views. In such cases, the PCB must meet automotive-grade standards, like AEC-Q100 for the components and IPC-6012 for the board. This adds cost but ensures reliability in harsh environments. The bottom line is that designing a dual screen HDMI to MIPI DSI adapter is a rewarding project that requires attention to detail in every aspect of the PCB layout, from impedance control to thermal management. With the right components and careful routing, you can achieve a stable, high-performance adapter that works with a wide range of displays.